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| quad, low power, 12 - bit, 180 msps, digital -to - analog converter and waveform generat or data sheet AD9106 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is g ranted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features highly integrated quad dac on - chip 4 096 12- bit pattern memory on - chip dds power dissipation at 3.3 v, 4 ma output 315 mw at 180 msps sleep mode: < 5 mw at 3.3 v supply voltage: 1.8 v to 3.3 v sfdr to nyquist 86 dbc at 1 mhz output 85 dbc at 10 mhz output phase n oise at 1 khz o ffset , 180 msps, 8 ma : ?140 dbc/hz differential current outputs: 8 ma max imum at 3.3 v small footprint 32 - lead , 5 mm 5 mm with 3. 5 mm 3. 6 mm exposed paddle lfcsp pb - free package applications medical instrumentation ultrasound transducer excitation portable instrumentati on signal generators, arbitrary waveform generators ge neral description the AD9106 txdac? and waveform generator is a high perform - ance quad dac integrating on - chip pattern memory for complex waveform genera tion with a direct digital synthesizer (dds). the dds is a 12 - bit output , up to 180 mh z master clock sinewave generator with a 24 - bit tuning word allowing 10.8 hz/ lsb frequency resolution. the dds has a single frequency output for all four dacs and indepen dent programmable phase shift outputs for each of the four dacs . s ram data can include directly generated stored waveforms, a mplitude modulation patterns applied to dds outputs , or dds frequency tuning words . an internal pattern control state machine al lows the user to program the pattern period for all four dacs as well as the start delay within the pattern period for the signal output on each dac channel . an spi interface is used to configure the digital waveform generator and load patterns into the s ram . there are gain adjustment factor s and offset adjustment s applied to the digital signals on their way into the four dacs . the AD9106 offers exceptional ac and dc performance and support s dac sampling rates up to 180 msps . the flexible power supply operating range of 1.8 v to 3.3 v and low power dissipation of the AD9106 make it well suited for portable and low power applications.
AD9106 data sheet rev. a | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 dc specifications (3.3 v) ............................................................ 4 dc specifications (1.8 v) ............................................................ 5 digital timing specifications (3.3 v) ........................................ 6 digital timing specifications (1.8 v) ........................................ 6 input/output signal specifications ............................................ 7 ac specifications (3.3 v) ............................................................ 8 ac specifications (1.8 v) ............................................................ 8 power supply voltage inputs and power dissipation .............. 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 terminology .................................................................................... 19 theory of operation ...................................................................... 20 spi port ........................................................................................ 21 dac transfer function ............................................................. 22 analog current outputs ........................................................... 22 setting i outfsx , dac gain .......................................................... 22 automatic i outfsx calibration ................................................... 23 clock input .................................................................................. 23 dac output clock edge ........................................................... 24 generating signal patterns ........................................................ 24 pattern generator programming ............................................. 25 dacx input data paths ............................................................. 25 dout function ......................................................................... 26 direct digital synthesizer (dds) ............................................. 26 sram ........................................................................................... 27 sawtooth generator ................................................................... 27 pseudo - random signal generator .......................................... 27 dc constant ............................................................................... 27 power supply notes ................................................................... 27 power - down capabilities .......................................................... 27 applications inform ation .............................................................. 28 signal generation examples ..................................................... 28 register map ................................................................................... 30 register descriptions ................................................................. 33 outline dimensions ....................................................................... 48 ordering guide .......................................................................... 48 revision history 2/13 rev. 0 to rev. a updated format .................................................................. universal changes to features section ............................................................ 1 changes to figure 1 .......................................................................... 3 deleted figure 20; renumbered sequentially ............................ 16 changes to figure 31 ...................................................................... 20 changes to table 13 ........................................................................ 22 d eleted recommendations w hen using an external reference section ............................................................................ 23 11/12 rev ision 0 : initial version data sheet AD9106 rev. a | page 3 of 48 functional block dia gram dac1 dac2 10k? i ref 100a 1.8v ldos 1v AD9106 ioutp1 ioutn1 avdd1 agnd ioutp2 ioutn2 dvdd dgnd dldo1 sdio sclk reset refio fsadj1 fsadj2/cal_sense clkvdd clkgnd clkn cs cldo clkp 1.8v ldo dac3 dac4 ioutp3 ioutn3 avdd2 ioutp4 ioutn4 r set3 16k? r set4 16k? fsadj4 fsadj3 dpram address 1, 2 address 3, 4 gain1 offset1 dac1 dac2 dac3 dac4 dac3 to dac4 timers + state machines dac1 to dac2 timers + state machines start addr start dly stop addr start addr start dly stop addr dac clock dac clock trigger sdo/sdi2/dout dldo2 dds tuning word phase1 phase2 phase3 phase4 dac clock dds1 dds2 dds3 dds4 sawtooth1 constant1 dds1 random1 spi interface gain2 offset2 gain3 offset3 gain4 offset4 band gap r set1 16k? r set2 16k? clock dist 11121-001 figure 1 . AD9106 data sheet rev. a | page 4 of 48 specifications dc specifications (3.3 v) t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v; i nternal cldo, dldo1 , and dldo2; i outfs = 4 ma, maximum sample rate, unles s otherwise noted. table 1. parameter min typ max unit resolution 12 bits accuracy at 3.3 v differential nonlinearity (dnl) 0.4 lsb integral nonlinearity (inl) 0.5 lsb dac outputs offset error .00025 % of f sr gain error internal reference no automatic i outfs calibration ? 1.0 + 1.0 % of f sr full - scale output current 1 at 3.3 v 2 4 8 ma output resistance 200 m? output compliance voltage ? 0.5 + 1.0 v crosstalk, dac to dac (f out = 10 mhz) 96 dbc crosstalk, dac to dac (f out = 60 mhz) 82 dbc dac temperature drift gain with internal reference 251 ppm/c internal reference voltage 119 ppm/c reference output internal reference voltage with avdd = 3.3 v 0. 8 1.0 1. 2 v output resistance 10 k ? reference input voltage compliance 0.1 1.25 v in put resistance external , reference mode 1 m ? dac matching gain matching no automatic i outfs calibration 0.75 % of fsr 1 based on use of 8 k ? e xternal xr set resistors. data sheet AD9106 rev. a | page 5 of 48 dc specifications (1 .8 v) t min to t max , avdd = 1.8 v , dvdd = dldo1 = dldo2 = 1.8 v, clkvdd = cldo = 1.8 v, i outfs = 4 ma , m aximum sample rate, unless otherwise noted . table 2. parameter min typ max unit resolution 12 bits accuracy at 1.8 v differential nonlinearity (dnl) 0.4 lsb integral nonlinearity (inl) 0.4 lsb dac outputs of fset error .00025 % of fsr gain error internal reference no automatic i outfs calibration ? 1.0 + 1.0 % of fsr full - scale output current 1 at 1.8 v 2 4 4 ma output resistance 200 m? output compliance voltage ? 0.5 +1.0 v crosstalk, dac to dac (f out = 30 mhz) 94 db crosstalk, dac to dac (f out = 60 mhz) 78 db dac temperature drift gain 228 ppm/c reference voltage 131 ppm/c reference output internal reference voltage with avdd = 1.8 v 0.8 1.0 1.2 v output resistance 10 k ? reference input voltage compliance 0.1 1.25 v input resistance external, reference mode 1 m ? dac matching gain matching no automatic i outfs calibration 0.75 % of fsr 1 based on use of 8 k ? e xternal xr set resistor s. AD9106 data sheet rev. a | page 6 of 48 digital timing specifications (3.3 v) t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v; internal cldo, dldo1 , and dldo2; i outfs = 4 ma, maximum sample rate, unless otherwise noted. table 3. parameter min typ max unit dac clock input (clkin) maximum clock rate 180 msps serial peripheral interface maximum clock rate (sclk) 80 mhz minimum pulse width high 6.25 ns minimum pulse width low 6.25 ns setup time sdio to sclk 4.0 ns hold time sdio to sclk 5.0 ns output data valid sclk to sdo or sdio 6.2 ns setup time e e aa to sclk cs 4.0 ns digital timing specifications (1.8 v) t min to t max , avdd = 1.8 v, dvdd = dldo1 = dldo2 = 1.8 v, clkvdd = cldo = 1.8 v, i outfs = 4 ma, maximum sample rate, unless otherwise noted . table 4. parameter min typ max unit dac clock input (clkin) maximum clock rate 180 msps serial peripheral interface maximum clock rate (sclk) 80 mhz minimum pulse width high 6.25 ns minimum pulse width low 6.25 ns setup time sdio to sclk 4.0 ns hold time sdio to sclk 5.0 ns output data valid sclk to sdo or sdio 8.8 ns setup time a a cs e e aa to sclk 4.0 ns data sheet AD9106 rev. a | page 7 of 48 input/output signal specification s table 5. parameter test conditions / comments min typ max unit cmos input logic level (sclk, a a cs e e aa , sdio, sdo/sdi2/dout, a a reset e e aa , a a trigger e e aa ) input v in logic high d vdd = 1.8 v 1.53 v d vdd = 3.3 v 2.475 v input v in logic low d vdd = 1.8 v 0.27 v d vdd = 3.3 v 0.825 v cmos outp ut logic level (sdio, sdo/sdi2/dout ) output v out logic high d vdd = 1.8 v 1.79 v d vdd = 3.3 v 3.28 v output v out logic low d vdd = 1.8 v 0.25 v d vdd = 3.3 v 0.625 v dac clock input (clkp, clkn) minimum peak - to - peak differential in put voltage , v clkp /v clkn 150 mv maximum voltage at v clkp or v clkn v dvdd v minimum voltage at v clkp or v clkn v dgnd v c ommon - mode voltage generated on c hip 0.9 v AD9106 data sheet rev. a | page 8 of 48 ac specifications (3.3 v) t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3 .3 v; internal cldo, dldo1 , and dldo2; i outfs = 4 ma, maximum sample rate, unless otherwise noted. table 6. parameter min typ max unit spurious free dynamic range (sfdr) f dac = 180 msps , f out = 10 mhz 86 dbc f dac = 180 ms ps, f out = 50 mhz 73 dbc two - tone intermodulation distortion (imd) f dac = 180 msps , f out = 10 mhz 92 dbc f dac = 180 msps , f out = 50 mhz 77 dbc nsd f dac = 180 msps , f out = 50 mhz ?167 dbm/hz phase noise at 1 khz from carrier f dac = 180 msps , f out = 10 mhz ?135 dbc/hz dynamic performance output settling time, full scale output step (to 0.1%) 1 31.2 ns trigger to output delay, f dac = 180 msps 2 96 ns rise time, fu ll- scale swing 1 3.25 ns fall time, full - scale swing 1 3.26 ns 1 based on the 85 ? r esistors from dac output terminals to ground. 2 start d elay = 0 f dac clock cycles. a c specifications (1.8 v) t min to t max , avdd = 1.8 v , dvdd = dldo1 = dldo2 = 1.8 v, c lkvdd = cldo = 1.8 v, i outfs = 4 ma , maximum sample rate, unless otherwise noted . table 7. parameter min typ max unit spurious free dynamic range (sfdr) f dac = 180 msps , f out = 10 mhz 83 dbc f dac = 180 msps , f out = 50 mhz 74 dbc two - tone intermodulation distortion (imd) f dac = 180 msps , f out = 10 mhz 91 dbc f dac = 180 msps , f out = 50 mhz 83 dbc nsd f dac = 180 msps , f out = 50 mhz ?163 dbm/hz phase noise at 1 khz from carrier f dac = 180 msps , f out = 10 mhz ?135 dbc/hz dynamic performance output settling time (to 0.1%) 1 31.2 ns trigger to output delay, f dac = 180 msps 2 96 ns rise time 1 3.25 ns fall time 1 3.26 ns 1 based on the 85 ? r esistors from dac output terminals to ground. 2 start d elay = 0 f dac clock cycles . data sheet AD9106 rev. a | page 9 of 48 power supply voltage inputs and power dis sipation table 8. parameter test conditions/comments min typ max unit a nalog s upply voltages avdd1, avdd2 1.7 3.6 v clkvdd 1.7 3.6 v cldo on- chip ldo not in u se 1.7 1.9 v digital supply voltages dvdd 1.7 3.6 v dldo1, dldo2 on- chip ldo not in u se 1.7 1.9 v power co nsumption avdd = 3.3 v, dvdd = 3.3 v, c lk v dd = 3.3 v, i nternal cldo, dldo1 , and dldo2 f dac = 180 msps, pure cw sine wave 12.5 mhz (dds o nly) , all four dacs 315.25 mw i avdd 28.51 ma i dvdd dds o nly cw sine wave output 60.3 ma ram o nly 50% duty cycle fs pulse output 27.1 ma d ds and ram o nly 50% duty cycle sine wave output 39.75 ma i clkvdd 6.72 ma power- down mode ref_pdn = 0 , dacs sleep, clk power down, external clk, and supplies on 4.73 mw power consumption avdd = 1.8 v, dvdd = dldo1 = dldo2 = 1.8 v, clkvdd = cldo = 1.8 v f dac = 180 msps , pure cw sine w ave 12.5 mhz (dds o nly) 167 mw i avdd 28.14 ma i dvdd 0.151 ma i d ldo2 dds only cw sine wave output 53.75 ma ram o nly 50% duty cycle fs pulse output 17.78 ma dds and ram o nly 50% duty cycle sine wave output 35.4 ma i d ldo1 4.0 ma i clkvdd 0.0096 ma i cldo 6.6 ma power- down mode ref_pdn = 0 , dacs sleep, clk power down, external clk, and supplies on 1.49 mw AD9106 data sheet rev. a | page 10 of 48 a bsolute maximum rati ngs table 9. parameter rating avdd1, avdd2, dvdd to agnd, dgnd, clkgnd ?0.3 v to +3.9 v clkvdd to agnd, dgnd, clkgnd ?0.3 v to +3.9 v cldo, dldo1, dldo2 to agnd, dgnd, clkgnd ?0.3 v to +2.2 v agnd to dgnd, clkgnd ?0.3 v to +0.3v dgnd to agnd, clkgnd ?0.3 v to +0.3 v clkgnd to agnd, dgnd ?0.3 v to +0.3 v a a cs e e aa , sdio, sclk, sdo/sdi2/dout, a a reset e e aa , a a trigger e e aa to dgnd ?0.3 v to dvdd + 0.3 v clkp, clkn to clkgnd ?0.3 v to clkvdd + 0.3 v refio to agnd ?1.0 v to avdd + 0.3 v ioutp1, ioutn1, ioutp2, ioutn2, ioutp3, ioutn3, ioutp4, ioutn4 to agnd ?0.3 v to dvdd + 0.3 v fsadj1, fsadj2/cal_sense, f4dj3, fsadj4 to agnd ?0.3 v to avdd + 0.3 v junction temperature 125 c storage temperature ?65 c to +150 c stresses above those listed under absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating c onditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a standard circuit board for surface - mount packages. j c is measured from the solder side (bottom) of the package. table 10 . thermal resistance package ty pe ja jb jc unit 32- lead lfcsp with exposed paddle 30.18 6.59 3.84 c/w esd caution data sheet AD9106 rev. a | page 11 of 48 pin configuration and function descripti ons 24 fsadj2/cal_sense 23 clkvdd 22 cldo 21 clkp 20 clkn 19 clkgnd 18 refio 17 fsadj4 1 2 3 4 5 6 7 8 sclk sdio dgnd dldo2 dvdd dldo1 sdo/sdi2/dout cs 9 10 11 12 13 14 15 16 reset ioutp4 ioutn4 avdd2 ioutn3 ioutp3 agnd fsadj3 32 31 30 29 28 27 26 25 trigger ioutp2 ioutn2 avdd1 ioutn1 ioutp1 agnd fsadj1 top view (not to scale) AD9106 notes 1. the exposed pad must be connected to dgnd. 11 121-002 figure 2 . pin configuration table 11 . pin function descri ptions pin no. mnemonic description 1 sclk spi clock input . 2 sdio spi d ata input/output. primary bidirectional data line for the spi port. 3 dgnd digital g round . 4 dldo2 1.8 v internal digital ldo1 output . when the internal digital ldo1 is enabled, this pin should be bypassed with a 0.1 f capacitor. 5 dvdd 3.3 v external digital power supply . dvdd defines the level of the digital interface of the AD9106 (spi interface). 6 dldo1 1.8 v internal digital l do2 outputs. when the internal digital ldo2 is enabled, this pin should be bypassed with a 0.1 f capacitor. 7 sdo/sdi2/dout digital i/o pin. in 4- wire spi mode, this pin outputs the data from the spi. in double spi mode, this pin is a second data input l ine, sdi2, for the spi port used to write to the sram. in data out put mode, this terminal is a programmable pulse output . 8 a a cs e e spi port chip select, active low. 9 a a reset e e active low reset pin . resets registers to their default values . 10 ioutp4 dac4 current output , positive side. 11 ioutn4 dac4 current output , negative side. 12 avdd2 1.8 v to 3.3 v p ower supply input for dac3 and dac4. 13 ioutn3 dac 3 current output , negative side. 14 ioutp3 dac 3 current output , positive side. 15 agnd analog ground . 16 fsadj3 external full - scale current output adjust for dac3 . 17 fsadj4 external full - scale current output adjust for dac4 . 18 refio dac voltage reference input/output . 19 clkgnd clock ground . 20 clkn clock inp ut, negative side . 21 clkp clock input, positive side . 22 cldo clock power supply o utput ( internal regulator in u se), clock power supply i nput (internal regulator b ypassed) . 23 clkvdd clock power supply input . 24 fsadj2/c al _sense external full - scale cu rrent output adjust for dac2 or sense i nput for automatic i outfs calibration . 25 fsadj1 external full - scale current output adjust for dac1 or full - scale current output adjust reference for automatic i outfs calibration . 26 agnd analog ground . 27 ioutp1 dac1 current output , positive side. AD9106 data sheet rev. a | page 12 of 48 pin no. mnemonic description 28 ioutn1 dac1 current output , negative side. 29 avdd1 1.8 v to 3.3 v power supply i nput for dac1 and dac2. 30 ioutn2 dac2 current output , negative side. 31 ioutp2 dac2 current output , positive side. 32 a a trigger e e pattern trigger input . epad e xposed pad. the exposed pad must be connected to dgnd . data sheet AD9106 rev. a | page 13 of 48 typical performance characteristics avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i nternal cldo, dldo1 , and dldo2 . ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 level (dbc) f out (mhz) sfdr third (dbc) second (dbc) 11 121-003 figure 3 . sfdr, 2nd and 3rd harmonics at i outfs = 8 m a vs. f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 level (dbc) f out (mhz) sfdr third (dbc) second (dbc) 11 121-004 figure 4 . sfdr, 2nd and 3rd harmonics at i outfs = 4 ma vs . f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 level (dbc) f out (mhz) sfdr third (dbc) second (dbc) 11 121-005 figure 5 . sfdr, 2nd and 3rd harmonics at i outfs = 2 ma vs . f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 sfdr (dbc) f out (mhz) 8ma 4ma 2ma 11 121-006 figure 6. sfdr at three i outfs vs . f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 sfdr (dbc) f out (mhz) ?40c +25c +85c 11 121-007 figure 7 . sfdr at three temperatures vs. f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 sfdr (dbc) f out (mhz) 50mhz 100mhz 180mhz 11 121-008 figure 8 . sfdr at three f dac vs . f out AD9106 data sheet rev. a | page 14 of 48 start 0hz vbw 5.6khz stop 80mhz sweep 3.076s (601pts) ref ?5dbm atten 18db mkr3 41.73mhz ?90.031dbm 1 2 3 marker trace type x-axis amplitude 1 (1) freq 13.87mhz ?11.13dbm 2 (1) freq 27.87mhz ?88.70dbm 3 (1) freq 41.73mhz ?90.03dbm 11 121-009 figure 9 . output spectrum f ou t = 13.87 mh z ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 8070 imd (dbc) f out (mhz) 50mhz 100mhz 180mhz 11 121-010 figure 10 . imd vs . f out , three f dac values ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 8070 imd (dbc) f out (mhz) 8ma 4ma 2ma 11 121-0 11 figure 11 . imd vs . f out , three i outfs values ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 8070 imd (dbc) f out (mhz) dac4 dac3 dac2 dac1 11 121-012 figure 12 . imd vs . f out , all four dacs ?130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 0 10 20 30 40 50 60 908070 nsd (dbm/hz) f out (mhz) 8ma 4ma 2ma 11 121-013 figure 13 . nsd vs. f out , three i outfs values ?130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 0 10 20 30 40 50 60 908070 nsd (dbm/hz) f out (mhz) ?40c +25c +85c 11 121-014 figure 14 . nsd vs . f out at three temperatures data sheet AD9106 rev. a | page 15 of 48 0.4 0.3 0.2 0.1 0 ?0. 1 ?0.2 ?0.3 0 500 1000 1500 2000 2500 3000 4500 4000 3500 dnl (lsb) code 2ma 4ma 8ma 11 121-015 figure 15 . dnl , three i outfs values 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 0 500 1000 1500 2000 2500 3000 4500 4000 3500 inl (lsb) code 2ma 4ma 8ma 11 121-016 figure 16 . inl, three i outfs values ?80 ?100 ?120 ?140 ?160 ?180 100 10m 1m 100k 10k 1k phase noise (dbc/hz) offset (hz) f s = 175mhz, 10mhz f s = 175mhz, 10.9375mhz f s = 175mhz, 20mhz 11 121-017 f igure 17 . phase noise AD9106 data sheet rev. a | page 16 of 48 avdd = 1.8 v , dvdd = dldo1 = dldo2 = 1 . 8 v, clkvdd = cldo = 1.8 v . ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 level (dbc) f out (mhz) sfdr third (dbc) second (dbc) 11 121-018 figure 18 . sfdr, 2nd and 3rd harmonics at i outfs = 4 ma vs . f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 level (dbc) f out (mhz) sfdr third (dbc) second (dbc) 11 121-019 figure 19 . sfdr, 2nd and 3rd harmonics at i outfs = 2 ma vs . f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 sfdr (dbc) f out (mhz) 4ma 2ma 11 121-021 figure 20 . sfdr at t wo i outfs vs . f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 sfdr (dbc) f out (mhz) ?40c +25c +85c 11 121-022 figure 21 . sfdr at three temperatures vs. f out ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 70 sfdr (dbc) f out (mhz) 50mhz 180mhz 180mhz 11 121-023 figure 22 . sfdr at three f d ac vs . f out start 0hz vbw 5.6khz stop 80mhz sweep 3.076s (601pts) ref ?5dbm atten 18db mkr3 41.73mhz ?88.255dbm 2 3 marker trace type x-axis amplitude 1 (1) freq 13.87mhz ?11.13dbm 2 (1) freq 27.87mhz ?89.05dbm 3 (1) freq 41.73mhz ?88.25dbm 1 11 121-024 figure 23 . output spectrum f out = 13.87 mh z data sheet AD9106 rev. a | page 17 of 48 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 8070 imd (dbc) f out (mhz) 180mhz 100mhz 50mhz 11 121-025 figure 24 . imd vs . f out , three f out values ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 8070 imd (dbc) f out (mhz) 4ma 2ma 11 121-026 figure 25 . imd vs . f out , t wo i outfs values ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 0 10 20 30 40 50 60 8070 imd (dbc) f out (mhz) dac4 dac3 dac2 dac1 11 121-027 figure 26 . imd vs . f out , all four dacs ?130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 0 10 20 30 40 50 60 908070 nsd (dbm/hz) f out (mhz) 4ma 2ma 11 121-028 figure 27 . nsd vs. f out , two i outfs values ?130 ?135 ?140 ?145 ?150 ?155 ?160 ?165 ?170 0 10 20 30 40 50 60 908070 nsd (dbm/hz) f out (mhz) ?40c +85c +25c 11 121-029 figure 28 . nsd vs . f out at three temperatures 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 0 500 1000 1500 2000 2500 3000 4500 4000 3500 dnl (lsb) code 2ma 4ma 11 121-030 figure 29 . dnl , three i outfs values AD9106 data sheet rev. a | page 18 of 48 0.5 0.4 0.3 0. 2 0.1 0 ?0.1 ?0.2 ?0.3 0 500 1000 1500 2000 2500 3000 4500 4000 3500 inl (lsb) code 2ma 4ma 11 121-031 figure 30 . inl, t wo i outfs values data sheet AD9106 rev. a | page 19 of 48 terminology linearity error (integral nonlinearity or inl) inl is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zer o to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a digital - to - analog converter is monotonic if the output eith er increases or remains constant as the digital input increases. offset error offset error is the deviation of the output current from the ideal of zero. for ioutpx , 0 ma output is expected when the inputs are all 0s. for ioutnz , 0 ma output is expected wh en all inputs are set to 1. gain error gain error is the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1, minus the output when all inputs are set to 0. the ideal gain is calcula ted using the measured vref. therefore, the gain error does not include effects of the reference. output compliance voltage output compliance voltage is the range of allowable voltage at the output of a current output dac. operation beyond the maximum co mpliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offse t and gain drift, the drift is reported in ppm of full - scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection power supply rejection is the maximum change in the full - scale output as the supplies are var ied from nominal to minimum and maximum specified voltages. settling time settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch im pulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in picovolt - seconds (pv -s). spurious - free dynamic range (sfdr) sfdr is the differenc e, in decibels (db), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. noise spectral density (nsd) noise spectral density is the average noise power normalized to a 1 hz bandwidth, with the dac conv erting and producing an output tone. AD9106 data sheet rev. a | page 20 of 48 theory of operation 11121-032 dac1 dac2 10k? i ref 100a 1.8v ldos 1v AD9106 ioutp1 ioutn1 avdd1 agnd ioutp2 ioutn2 dvdd dgnd dldo1 sdio sclk reset refio fsadj1 fsadj2/cal_sense clkvdd clkgnd clkn cs cldo clkp 1.8v ldo dac3 dac4 ioutp3 ioutn3 avdd2 ioutp4 ioutn4 r set3 16k? r set4 16k? fsadj4 fsadj3 dpram address 1, 2 address 3, 4 gain1 offset1 dac1 dac2 dac3 dac4 dac3 to dac4 timers + state machines dac1 to dac2 timers + state machines start addr start dly stop addr start addr start dly stop addr dac clock dac clock trigger sdo/sdi2/dout dldo2 dds tuning word phase1 phase2 phase3 phase4 dac clock dds1 dds2 dds3 dds4 sawtooth1 constant1 dds1 random1 spi interface gain2 offset2 gain3 offset3 gain4 offset4 band gap r set1 16k? r set2 16k? clock dist figure 31 . AD9106 block diagram figure 31 is a block diagram of the AD9106 . the AD9106 has four 12- bit current output dacs. the dacs use a single common voltage reference. an on - chip band gap reference is provided. o ptional ly , an off - chip voltage reference may be used . full - scale dac output current , also known as gain , is governed by the current , i ref . i ref is the current that flows through each i ref resistor. each dac has its own i ref set resistor. the se resistor s may be on or off chip at the discretion of the user . when on - chip r set resistors are in use dac gain accuracy can be improved by employing the products built in automatic gain calibration capability . auto - matic calibration may be used with the on - chip reference or an external refio voltage. a p rocedure for automatic gain calibration is presented in this section . the power supply rails for the AD9106 are avdd for analog circuits, clkvdd/ cldo for clock input receiver and dvdd/dldo1/dldo2 for digital i /o and for the on - chip digital data path . avdd, dvdd, and clkvdd can range from 1.8 v to 3.3 v nominal. dld o1, dldo2 , and cldo run at 1.8 v. if dvdd = 1.8 v, then dldo1 and dldo2 should both be connected to dvdd, with the on - chip ldos disabled. all three supplies are provided externally in this case. this also applies to clkvdd and cldo if clkvdd = 1.8 v. d igital signals input to the four dacs are generated by on - chip digital waveform generat ion resources. twelve - bit samples are input to each dac at the clkp/clkn sample rate from a dedicated digital data path. each dacs data path includes gain and offset corrections and a digital waveform source selection multiplexer. waveform sources are sram, direct digital synthesizer (dds), dds output amplitude modulat ed by sram data, a sawtooth generator, dc constant, and a pseudo - random sequence generator. the waveforms output by the source selection multiplexer have programmable pattern character - istics. the waveforms can be set up to be continuous, continuous pulsed (fixed pattern period and start delay within each pattern period), or finite pulsed (a set number of pattern periods are output, then the pattern stops). pulsed waveforms (finite or continuous) have a programmed pattern period and start delay. the wavefor m is present in each data sheet AD9106 rev. a | page 21 of 48 pulse period following the global (applies to all four dacs) programmed pattern period start and each dacs start delay . an spi port enables loading of data into sram and program - ming of all the control registers inside the device. s pi port the AD9106 provides a flexible, synchronous serial communi - cations (spi) port that allows easy interfacing to asics, fpgas , and industry standard microcontrollers. the interface allows read/write acce ss to all registers that configure the AD9106 and to the on - chip sram . it s data rate can be up to the sclk clock speed shown in table 3 and tabl e 4 . the spi interface operates as a standard synchronous serial communication port . e e aa is a low true chip select. when a a cs e e aa goes true , spi address and data tra n sfer begins . the first b it coming from the spi master on sdio is a read/ write indicator (high for read, low for write) . th e next 15 - bit s are the initial register address. the spi port automatically increments the register address if a a cs e e aa stays low beyond the first data word allowing writes to or reads f rom a set of contiguous addresses. cs table 12. command word msb lsb db15 db14 db13 db12 db2 db1 db0 r a a w e e a14 a13 a12 a2 a1 a0 when the first bit of this command byte is a logic low (r a a w e e aa bit = 0), the spi command is a write operation. in thi s case, sdio remains an input ( see figure 32 ). command cycle data transfer cycle cs sclk sdio a14 a13 a2 a1 a0 d15 n d14 n d13 n d3 n d2 n d1 n d0 n r/w 11 121-033 figure 32 . serial register interface timing, msb first write , 3 -w ire spi when t he first bit of this command byte is a logic high ( r a a w e e aa bit = 1), the spi command is a read operation. in this case , d ata is driven out of the spi port as shown in figure 33 and figure 34 . the spi communication finishes after the a a cs e e aa pin goes high. cs sclk sdio a14 a13 a2 a1 a0 d15 n d14 n d13 n d3 0 d2 0 d1 0 d0 0 r/w command cycle data transfer cycle 11 121-034 figure 33 . serial register inter face timing, msb first read, 3 -w ire spi cs sclk sdio sdo/ sdi2/ dout write r/w a14 a13 a2 a1 a0 d 15 d 1 d 0 r/w a14 a13 d15 n d0 n d1 0 d0 0 d15 n ? 1 d0 n ? 1 d15 n ? 2 a2 a1 a0 read 11 121-035 figure 34 . s erial register interface timin g, msb first read, 4 -w ire spi AD9106 data sheet rev. a | page 22 of 48 writing to on - chip sram the AD9106 includes an internal 4096 12 s ram . the sram address space is 0x6000 to 0x6fff of the AD9106 spi address map. double spi for write for sram the time to write data to the entire sram can be halved using the spi access mode shown in figure 35. t he sdo /sdi2/ dout line becomes a second serial data input line , doubling the achievable update rate of the on - chip s ram. sdo/sdi2/ dout is write - only in this mode. the entire sram can be written in (2 + 2 4096) 8/(2 f sclk ) seconds. cs sclk sdio sdo/ sdi2/ dout set waveform address to be read/written waveform pattern address1 = n waveform pattern data waveform data to be written waveform pattern address2 = m waveform pattern data r/w a14 a13 a2 a1 a0 d15 n d0 n d15 n ? 1 d0 n ? 1 d15 n ? 2 d1 0 d0 0 r/w = 0 always a14 a13 a2 a1 a0 d15 m d0 m d15 m ? 1 d0 m ? 1 d15 m ? 2 d1 n + 1 d0 n + 1 11 121-036 figure 35 . double spi write of sram data co nfiguration register update procedure most spi accessible registers are double buffered . an active register set controls operation of the AD9106 during pattern generation. a set of shadow registers stores updat ed register values. register updates can be written at any time and when the configuration update is complete, a 1 is written to the update bit in the ramupdate register. the update bit arms the register set for transfer from shadow registers to active reg isters. the AD9106 will perform this transfer automatically the next time the pattern generator is off. this procedure does not apply to the 4 k 12 sram. refer to the sram section for the sram update procedure. dac transfer functio n the AD9106 dacs provide fo ur differential current outputs: ioutp1/ioutn1, ioutp2/ioutn2, ioutp3/ioutn3 , and ioutp4/ioutn4. the dac output current equations ar e as follows: ioutp x = i outfsx xdac input code /2 12 (1) ioutnx = i outfsx ((2 12 ? 1) ? xdac i nput code )/2 12 (2) where: xdac input code = 0 to 2 12 ? 1 . i outfsx = f ull - scale current or dac gain set independently for each dac. i outfsx = 32 i irefx (3) where: i refx = v refio / xr set (4) i ref x is the current that flows through each i ref x resistor. each dac has its own i ref set resistor. i ref resistors may be on or off chip at the users discretion. when on - chip xr set resistors are in use , dac gain accuracy can be improved by employing the products built in automatic gain calibration capability . analog current output s optimum linearity and noise performance of dac outputs can be achieved when they are connected differentially to an amplifier or a transform er. in these configurations, common - mode signals at the dac outputs are rejected. the output compliance voltage s pecifications shown in table 1 and table 2 must be adhered to for the performance specifi cations in these tables to be met. setting i outfs x , dac gain as expressed in equation 3 and equation 4, dac gain ( i outfsx ) is a function of the reference voltage at the refio terminal and xr set for each dac . voltage reference the AD9106 contains an internal 1.0 v nominal band gap reference. the internal reference may be used. alternatively, it can be replaced by a more accurate off - chip reference. an external reference can provide tighter reference voltage t olerances and/ or lower temperature drift than the on - chip band gap . by default , the on - chip reference is powered up and ready to be used. when using the on - chip reference, t he refio terminal needs to be decoupled to agnd using a 0.1 f capacitor as shown in figure 36 . current scaling x32 AD9106 dacx i outfsx xr set 0.1f refio i refx avss fsadjx v bg 1.0v ? + 11 121-037 figure 36 . on -c hip reference with e xternal xr set r esistor table 13 summarizes reference connections and programming . table 13 . reference operation reference mode refio pin internal connect 0.1 f capacitor external connect off - chip reference data sheet AD9106 rev. a | page 23 of 48 programming internal v refio the internal refio voltage level is programmable . when the internal voltage reference is in use, the bgdr field in the lower six bits in register 0x03 adjust s the v refio level. this adds or subtracts up to 20% from the nominal band gap voltage on refio. t he voltage across the fsadjx resistors tracks this change. as a result , i ref x varies by the same amount. figure 37 shows v ref io vs. bgdr code for an on - chip reference with a default voltage (bgdr = 0x00) of 1.04 v. 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0. 95 0.90 0.85 0.80 0 8 16 24 32 40 48 56 code v refio (v) 11 121-038 figure 37 . typical v ref voltage vs. bgdr xr set r esistors xr set in equation 4 for each dac can be an internal resistor or a board level resistor of the users choosing connected to the appropriate fsadjx terminal. to make us e of on - chip xr set resistors, bit15 of r egister 0x0c, r egister 0x0b, r egister 0x0a , and register 0x09 for dac1, dac2, dac3 , and dac4 , respectively , are set to l ogic 1 . bits [4:0] of register 0x0c, register 0x0b, register 0x0a , and register 0x09 are used to manually program values for the on - chip xr set associated with dac1, dac2, dac3 , and dac4 , respectively. automatic i outfsx c alibration many applications require tight dac gain control. the AD9106 provides an automatic i outfsx calibration procedure used with on - chip xr set resistors only . t he voltage reference v refio can be the on - chip reference or an off - chip reference. the automatic calibration procedure does a fine adjustment of each internal xr set value and each current i ref x . when using automatic calibration the following board - level connections are required: 1. connect fsadj1 and fsadj 2/ cal_sense together . 2. a resistor should be installed between fsadj2/ cal_sense and ground. the value of this resistor should be r cal_sense = 32 v refio /i outfs where i outfs is the target full - scale current for all four dacs. automatic calibration uses an internal clock. this calibration clock is equal to the dac clock divided by the division factor cho sen by the cal_clk_div bits of r egister 0x 0d. each calibration cycle is between 4 and 512 dac clock cycles, depending on the value of cal_clk_div[2:0]. the frequency of the calibration clock should be less than 500 khz. to perform an automatic calibration, follow these steps : 1. s et the calibration ranges in r egisters 0x08[7:0] and 0x 0d[5:4] to their minimum value s to allow best calibration. 2. enable the calib ration clock bit , cal_clk_en, in r egister 0x 0d . 3. set the divider ratio for the calibration clock by setting cal_clk_div[2:0] bits in r egister 0x0d. the default is 512. 4. set the cal_mode_en bit in register 0x0d t o l ogic 1. 5. set the start_cal bit in r egister 0x000e to lo gic 1. this begins the calibration of the comparator, xr set and gain. 6. the cal_mode flag in r egister 0x000d wi ll go to l ogic 1 while the part is calibrating. th e cal_fin flag in register 0x0 e will g o to l ogic 1 when the calibration is complete. 7. set the start_cal bit in register 0x0 e to l ogic 0. 8. after calibration, verify that the overflow and underflow flags in register 0x0d are not set (bits[ 14: 8] ). if they are, change the corresponding calibration r ange to the next larger range and begin again at step 5 . 9. if no flag is set, read the dacx_rset_cal and dacx_again_cal values in the dacxrset[12:8] and dacxgain[14:8] registers , respectively , and write them into their corresponding dacxrset and dacx again r egisters. 10. r eset the cal_mode_en bit and the calib ration clock bit cal_clk_en in register 0x0 d to l ogic 0 to disable the calibration clock. 11. set the cal_mode_en bit in register 0x0d to lo gic 0. this sets the rset and gain control muxes towards the regular r egisters. 12. di sable the calib ration clock bit , cal_clk_en, in r egister 0x0 d. to reset the calibrati on, pulse th e cal_reset bit in register 0x 0d to l ogic 1 and logic 0, pulse the e e aa pin , or pulse the reset bit in the spiconfig registe r. reset clock input for optimum dac performance, the AD9106 clock input signal pair (clkp/ clkn) should be a very low jitter, fast rise time differential signal. th e clock receiver generates its own common - mode volt age requiring these t w o inputs to be ac - coupled . figure 38 shows the recommended interface to a number of analog devices, inc., lvds clock drivers that work well with the AD9106 . a 100 ? termination resistor and two 0 .1 f coupling capacitors are used. figure 40 shows an interface to an a nalog devices differential pecl driver. figure 41 show s a single -e nded - to - differential converter using a balun driving clkp/clkn, the preferred methods for clocking the AD9106 . AD9106 data sheet rev. a | page 24 of 48 100? 0.1f 0.1f 0.1f 0.1f 50?* 50?* clk clk *50? resistors are optional. clkn clkp AD9106 lvds driver clk+ clk? ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 11 121-039 figure 38 . differential lvds clock input in applications where the anal og output signals are at low frequencies, it is acceptable to drive the AD9106 clock input with a single - ended cmos signal. figure 39 shows such an interface. clkp is driven directly f rom a cmos gate, and the clkn pin is bypassed to ground with a 0.1 f c a pacitor in parallel with a 39 k? resistor. the optional resistor is a series termination. ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 0.1f clk clk 0.1f 0.1f clkn clkp AD9106 optional 100? 39k? cmos driver clk+ 50? 11 121-040 figure 39 . single - ended 1.8 v cmos sample clock ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515/ ad9516/ad9518 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 50 ?* 50 ?* clk clk *50 ? resistors are optional. clkn clkp AD9106 pecl driver clk+ clk? 11 121-041 figure 40 . differential pecl sample clock 0.1f 0.1f 0.1f schottky diodes: hsm2812 clk+ 50? clkn clkp mini-circuits ? adt1-1wt, 1:1z xfmr AD9106 11 121-042 figure 41 . transformer coupled clock dac o utput clock edge each of the four dacs can be configured independently to output samples on the rising or falling edge of the clkp/clkn c lock input by configuring the dacx_inv_clk bits in the clockconfig register. this functionality sets the dac output timing resolution at 1/(2 f clkp / clkn ). generating signal p a tterns the AD9106 can generate three types of signal patterns under control of its programmable pattern generator. x continuous waveforms x periodic pulse train waveforms that repeat indefinitely x periodic pulse train waveforms that repeat a finite number of times run bit setting t he run bi t in the pat_status register to 1 arms the AD9106 for pattern generation. clearing this bit shut s down the pattern generator as shown in figure 45 . trigger terminal a falling edge on the t rigger terminal starts the generation of a p attern. if run is set, the falling edge of trigger starts pattern generation. as shown in figure 43, the pattern generator state goes to pattern on a number of clkp/ clk n clock cyc les following the falling edge of t rigger. this delay is programmed in the pattern_delay bit field. the rising edge on the trigger terminal is a request for the term ination of pattern generation (s ee figure 44 ). pattern bit (read only) the read - only pattern bit in the pat_status register indicates , when set to 1 , that the pattern generator is in the pattern on state . a 0 indicates that the pattern generator is in the pattern off state. data sheet AD9106 rev. a | page 25 of 48 pattern types ? continuous w aveforms are o utput by some or all dacx for the duration of the pattern on state of the pattern generator. continuous waveforms ignore pattern periods. ? periodic pulse trains that repeat indefinitely are waveforms that are output once during each pattern period. pattern periods occur one after the other as long as t he pattern generator is in the pattern on state . ? periodic pulse trains that repeat a finite number of times are just like those that repeat indefinitely except that the waveforms are output during a finite nu mber of consecutive pattern periods. pattern executed pattern executed pattern executed trigger dac1 dac2 dac3 dac4 pattern_period start_dly1 start_dly2 start_dly4 start_dly3 data @ start_addr.1 data @ stop_addr.1 data @ start_addr.2 data @ stop_addr.2 data @ start_addr.3 data @ stop_addr.3 data @ start_addr.4 data @ stop_addr.4 11 121-043 figure 42 . periodic pulse trains output on all dacx pattern generator programmin g figure 44 shows periodic pulse train waveforms as seen at the output to each of the four dacx. the four waveforms are generated in each pattern period. each has its own start delay (start_dlyx), a delay between the start of each pattern period and the start of the waveform. the four dacx waveforms are the same digital signal stored in sram and multiplied by the dacx digital gain factor. the sram data is read using each dacx address counter simultaneously. setting pattern period two register bit field s are used to set the pattern period. the pat_period_base field in the pat_timebase register sets the number of clkp/n clock per pattern_period lsb. the pattern_period is programmed in the pat_period register. the longest pattern period available is 65535 16/f clkp/clk n . setting waveform start delay base the waveform start delay base is programmed in the start_d elay_base field of the pat_timebase register. each dacx has a start _dl yx register described in the dac x input data paths section . the start delay base determines how many clkp/ clk n clock cycles there are per start_delayx lsb. t su t dly = pattern_delay value + 1 pattern starts trigger clkp/ clkn pattern generator state run bit pattern genertaor off pattern genertaor on 11 121-044 figure 43 . trigger initiated pattern start with pattern delay pattern stops trigger clkp/ clkn pattern generator state pattern on pattern off t su 11 121-045 figure 44 . trigger rising edge initiated pattern st op pattern stops clkp/ clkn run bit pattern generator state pattern on pattern off 11 121-046 figure 45 . run bit driven pattern stop dac x input data paths each of the four dacx has its own digital data path. timing in the dacx data paths is governed by the pattern generator. each dacx data path includes a waveform selector, a waveform repeat controller, ram output and dds output multiplier (ram output can amplitude modulate dds output), ddsx cycle counter, dacx digital gain multiplier, and a dacx digital offset summer. AD9106 data sheet rev. a | page 26 of 48 dacx digital gain multiplier on its way into each dacx , the samples are multiplied by a 12- bit gain factor that has a range of 2.0. the se gain values are programmed in the dacx_dgain registers. dacx digital offset summer dacx inp ut samples are summed with a 12 - bit dc offset value as well. the dc offset values are programmed in the dacxdof registers. dacx waveform selectors waveform sele ctor inputs are ? dacx sawtooth generator output ? dacx pseudo random sequence generator output ? dacx dc constant generator output ? dacx pulsed, phase shifted dds sine wave output ? ram o utput ? dacx pulsed, phase shifted dds sine wave output amplitude modulated by ram output waveform selection for each dacx is made by programming the wavex_yconfig registers. dacx pattern period repeat controller the pattern_rpt bit in the pat_type register controls whether the pattern output auto repeats (periodic pulse train repe ats indefinitely) or r epeats a number of consecutive times defined by the dacx_repeat_cycle fields. the latter are periodic pulse trains that repeat a finite number of times. dacx, number of dds cycles each dacx input data path establishes the pulse width of the sine wave output from the single common dds in number of sine wave cycles. the cycle counts are programmed in dds_cycx registers. dacx dds phase shift each dacx input data path shifts the phase of the output of the single common dds. the phase shift is programmed using the ddsx_phase fields. d out function in applications where AD9106 dacs drive high voltage amplifiers, such as in ultrasound transducer array element driver signal chains, it can be usefu l to turn on and off each amplifier at precise times relative to the waveform generated by each AD9106 dac. the sdo/sdi2/dout terminal, can be configured to provide this function. one amplifier on/off strobe ca n be provided for all four dacs . the s pi interface needs to be configured in 3 - wire mode ( see figure 32 and figure 33) . this is accomplished by setting the spi3wi re or spi3wirem bits in the spi config reg ister. when spid _ rv or spi _ drvm of the spiconfig register is set to logic 1 , the sdo/sdi2/dout terminal provides the dout function. manually controlled dout if dout_mode = 0 in the dout_config register, dout can be turned on or off using the dout_val bit of that same register. pattern generator controlled dout figure 46 depicts the rising edge of a pattern generator controlled dout pulse. figure 47 shows the falling edge . p attern gen erator controlled dout is set by setting dout_mode = 1. then , the start delay is programmed in the dout_start _dly register and the stop delay is programmed into the dout_stop field of the dout_config register. dout goes high dout_start[15:0] cl kp/ clk n cycles after the falling e dge of the signal input to the t rigger terminal. dout stays high as long as a pattern is being generated. dout goes low dout_stop[3:0] clkp/ clk n cycles after the clock edge that causes pattern generation to stop. trigger clkp/ clkn dout delay= dout_start[15:0] clkp/clkn cycles dout t su 11 121-047 figure 46 . dout start sequence clkp/clkn pattern generator state dout pattern on pattern off pattern stops dout delay = dout_stop[3:0] clkp/clkn cycles 11 121-048 figure 47 . dout stop sequence direct digital synth esizer (dds) the direct digital synthesizer generates a sine wave that can be output on any of the four dacx. the dds is a glob al shared signal resource. it can generate one sinusoid at a frequency determined by its tuning word input. the tuning word is 24 bits wide. the resolution of dds tuning is f clkp/clk n /2 24 . the dds output frequency is dds_tw f clkp/clk n /2 24 . the dds tunin g word is programmed using one of two methods. for a fixed frequency , ddstw_msb and ddstw_lsb are programmed with a constant. when the frequency of the dds needs to change within each pattern period , a sequence of values stored in sram is combined with a selection of ddstw_msb bits to form the tuning word. data sheet AD9106 rev. a | page 27 of 48 sram the AD9106 4k 12 sram can contain signal samples, amplitude modulation patterns, lists of dds tuning words , or lists of dds output phase offset words . data is written to and read from the memory via the spi port as long as the sram is not actively engaged in pattern generation (run = 0) . to write to sram , set up the pat_status register as follows: ? buf_read = 0 ? mem_access = 1 ? run = 0 to read data from s ram , set up the pat_status as follows: ? buf_read = 1 ? mem_access = 1 ? run = 0 the spi port address space for sram is location 0x6000 through 0x6fff. sram can be accessed using any of the spi operating modes shown in figure 32 throug h figure 35. using the spi modes of operation shown in figure 33 and figure 34 , the entire sram can be written in (2 + 2 4096) 8/f sclk seconds. the sram is a shared signal ge neration resource. data from this one 4 k 12 memory can be used to generate signals for all four dac . when the pat_status register run bit = 1 (pattern generation enabled), each dacx data path has its own sram address counter. each address counter has i ts own start_addrx and stop_addrx. during each pattern period, data is read from ram after the start_delayx period and while the each address counter is incrementing. sram is read simultaneously by all four dacx data paths. incrementing pattern generation mode sram address counters each of the sram address counters can be programmed to be incremented by clkp/ clk n (default) or by the rising edge of the ddsx msb. ddsx[11:0] are the dds output samples for a given dacx. the dds_msb_enx bits in the ddsx_config register make this selection. as an example, ddsx msb could be used to c lock the address counter when generating a chirp waveform from the dds using a list of tuning words in sram. each frequency setting dwells for one dds output sinewave cycle. s awtooth generator there is a separate s awtooth signal generator for each dacx . when the sawtooth is selected in any of the prestore_selx fields in the wav4_3conf ig or wav2_1 config registers , the appropriate sawtooth generator is connected to the desired dacx dig ital data path . sawtooth types, shown in figure 48 , are selected using the saw_typex fields in the sawx_yconfig registers. the number of samples per sawtooth waveform step is programmed in each saw_stepx field. positive sawtooth negative sawtooth triangle wave 11 121-049 figure 48 . sawt o oth patterns pseudo - random signal generator the pseudo - random noise generator generates a noise signal on each dacx output if pseudo - random sequence is selected in any of the prestore_selx fields in the wav4_3config or wav2_1 co nfig registers. the pseudo - random noise signals are generated as continuous waveforms only. dc constant a programmable dc current between 0.0 and i out fsx can be generated on each dacx if the c onstant v alue in selected in any of the prestore_selx fields of the wav4_3config or wav2_1 config registers. dc constant currents are generated as continuous waveforms only. the dc current level is programmed by writing to the dacx_const field in the appropriate dacx_cst register. power s uppl y notes the AD9106 supply rails are specified in table 9. the AD9106 includes three on - chip linear regulators. the supply rails driven by the se regulators are ru n at 1.8 v. two usage rules fo r these regulators follow. ? when clkvdd is 2.5 v or higher , the 1.8 v on - chip cldo regulator may be used. if clkvdd = 1.8 v, then the cldo regulator must be disabled by setting the pdn _ldo_clk bit in the powerconfig register. c lkvdd and cldo are connected to gether . ? when dvdd is 2.5 v or higher , the 1.8 v on - chip dldo1 and dldo2 regulators may be used. if dvvd is 1.8 v, t h e dldo1 and dldo2 regulators must be disabled by setting the pdn_ldo_dig1 and pdn_ldo_dig2 bits in the powerc onfig register. dvdd, dldo1, and dldo2 are connected to gether . power - down capabilities the powerconfig register allows the user to place the AD9106 in a reduced power dissipation configuration while the clkp/ clkn input is running and the power supplies are on. dac1, dac2, dac3, and dac4 can all be put to sleep by setting the dacx_sleep bits in the powerconfig register . clocking of the waveform generator and the dacs can be turned off by setting the clk_pdn bi t in the clockconfig register. taking these actions places the AD9106 in the power - down mode specified in tabl e 8 . AD9106 data sheet rev. a | page 28 of 48 applications in formation signal generation ex amples AD9106 waveform and pattern generation examples are provided in this section . figure 49 shows a different waveform being generated by each dacx. the waveforms are all stored in the 4 k 12 sram in d ifferent segments. dacx path address counters access the sram simultaneously. each waveform is repeated once during each pattern period. in each pattern period a start delay is executed, then the pattern is read from sram. pattern executed pattern executed pattern executed trigger dac1 dac2 dac3 dac4 pattern_period start_dly1 start_dly2 start_dly4 start_dly3 data @ start_addr1 data @ stop_addr1 data @ start_addr2 data @ stop_addr2 data @ start_addr3 data @ stop_addr3 data @ start_addr4 data @ stop_addr4 11 121-050 figure 49 . pattern using different waveforms stored in sram figure 50 shows pulsed sine waves generated by each dacx. the dds generates a sine wave at a programmed frequency. each dacx channel is programmed with a start delay and a num ber of sine wave cycles to output. 11 121-051 dac1 dac2 dac3 dac4 start_dly1 #cycles1 start_dly2 #cycles2 start_dly3 start_dly4 #cycles3 #cycles4 pattern_period figure 50 . pulsed sine w ave s in pattern periods figure 51 shows a pulsed sinewave generated by dac1 and each of the three available sawtooth wave shapes generated by dac2, dac3, and dac4 in successive pattern periods with start delay. 11 121-052 dac1 dac2 dac3 dac4 start_dly1 start_dly2 start_dly3 start_dly4 #cycles1 pattern_period figure 51 . pulsed sinew aves and sawtooth waveforms in pattern periods data sheet AD9106 rev. a | page 29 of 48 figure 52 shows all dacx outputting sine waves modulated by an amplitude envelope. the sine wave is generated by the dds and the amplitude envelope is stored in sram. different start delays and digital gain multipliers are applied by each dacx input data path. 11 121-053 dac1 dac2 dac3 dac4 start_dly1 start_dly2 start_dly3 start_dly4 pattern_period data @ start_addr1 data @ stop_addr1 data @ start_addr2 data @ stop_addr2 data @ start_addr3 data @ stop_addr3 data @ start_addr4 data @ stop_addr4 figure 52 . dds output amplitude m odulated by ram envelope figure 53 and figure 54 show the four dacs generating continuous waveforms. one with start delays, one without. 11 121-054 dac1 dac2 dac3 dac4 start_dly1 start_dly2 start_dly3 start_dly4 figure 53 . waveform s with start delay s 11 121-055 dac1 dac2 dac3 dac4 figure 54 . waveform s without start delay s AD9106 data sheet rev. a | page 30 of 48 register map table 14 . register summary addr (hex) register name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r e e w 0x00 spic onfig [15:8] lsbfirst spi3wire reset doublespi spi_drv dout_en reserved[3:2] 0x0 0 r a a w e e [7:0] reserved[1:0] dout_enm spi_drvm doublespim resetm spi3wirem lsbfirstm 0x01 powerconfig [15:8] reserved clk_ldo_stat dig1_ldo_stat dig2_ldo_ stat pdn_ldo_clk 0x0 0 r a a w e e [7:0] pdn_ldo_dig1 pdn_ldo_dig2 ref_pdn ref_ext dac1_sleep dac2_sleep dac3_sleep dac4_sleep 0x02 clockconfig [15:8] reserved [15:12] dis_clk1 dis_clk2 dis_clk3 dis_clk4 0x00 r a a w e e [7:0] dis_dclk clk_sleep clk_pdn eps dac1_inv_clk dac2_inv_clk dac3_inv_clk dac4_inv_clk 0x03 refadj [15:8] reserved[9:2] 0x0 0 r a a w e e [7:0] reserved[1:0] bgdr 0x04 dac4again [15:8] reserved dac4_gain_cal 0x0 0 r a a w e e [7:0] reserved dac4_gain 0x05 dac3again [15:8] reserved dac3_gain_cal 0x0 0 r a a w e e [7:0] reserved dac3_gain 0x06 dac2again [15:8] reserved dac2_gain_cal 0x0 0 r a a w e e [7:0] reserved dac2_gain 0x07 dac1again [15:8] reserved dac1_gain_cal 0x00 r a a w e e [7:0] reserved dac1_gain 0x08 dacxrange [15:8] reserved 0x0 0 r a a w e e [7:0] dac4_gain_rng dac3_gain_rng dac2_gain_rng dac1_gain_rng 0x09 dac4rset [15:8] dac4_rset_en reserved dac4 _rset_cal 0x 000a r a a w e e [7:0] reserved dac4_rset 0x0a dac3rset [15:8] dac3_rset_en reserved dac3_rset_cal 0x 000a r a a w e e [7:0] reserved dac3_rset 0x0b dac2rset [15:8] dac2_rset_en reserved dac2_rset_cal 0x 000a r a a w e e [7:0] reserved dac2_rset 0x0c dac1rset [15:8] dac1_rset_en reserved dac1_rset_cal 0x 000a r a a w e e [7:0] reserved dac1_rset 0x0d calconfig [15:8] reserved comp_offset _of comp_offset _uf rset_cal_of rset_cal _uf gain_cal_of gain_cal_uf cal_reset 0x0 0 r a a w e e [7:0] cal_mode cal_mode_en comp_cal_rng cal_clk_en cal_clk_div 0x0e compoffset [15:8] reserved comp_offset_cal 0x00 r a a w e e [7:0] reserved cal_fin start_cal 0x1d r amupdate [15:8] reserved[14:7] 0x0 0 r a a w e e [7:0] reserved[6:0] ramupdate 0x1e pat_status [15:8] reserved[12:5] 0x00 r a a w e e [7:0] reserved[3:0] buf_read mem_access pattern run 0x1f pat_type [15:8] reserved[14:7] 0x00 r a a w e e [7:0] reserved[6:0] pattern_rpt 0x20 pattern_dly [15:8] pattern_delay[15:8] 0x 000e r a a w e e [7:0] pattern_delay[7:0] 0x22 dac4dof [15:8] dac4_dig_offset[11:4] 0x 00 r a a w e e [7:0] dac4_d ig_offset[3:0] reserved 0x23 dac3dof [15:8] dac3_dig_offset[11:4] 0x00 r a a w e e [7:0] dac3_dig_offset[3:0] reserved 0x24 dac2dof [15:8] dac2_dig_offset[11:4] 0x0 0 r a a w e e [7:0] dac2_dig_offset[3:0] reserved 0x25 dac1dof [15:8] dac1_dig_offset[11:4] 0x0 0 r a a w e e [7:0] dac1_dig_offset[3:0] reserved 0x26 wav4_3config [15:8] reserved prestore_sel4 reserved wave_sel4 0000 r a a w e e [7:0] reserved prestore_sel3 reserved wave_sel3 0x27 wav2_1config [15:8] reserved prestore_sel2 mask_dac4 ch2_add wave_sel2 0x0 0 r a a w e e [7:0] reserved prestore_sel1 mask_dac3 ch1_add wave_sel1 data sheet AD9106 rev. a | page 31 of 48 addr (hex) register name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r a a w e e 0x28 pat_timebase [15:8] reserved hold 0x0111 r a a w e e [7:0] pat_period_base start_delay_base 0x29 pat_period [15:8] pattern_period[15:8] 0x8000 r a a w e e [7:0] pattern_period[7:0] 0x2a dac4_3patx [15:8] dac4_repeat_cycle 0x0101 r a a w e e [7:0] dac3_repeat_cycle 0x2b dac2_1patx [15:8] d ac2_repeat_cycle 0x0101 r a a w e e [7:0] dac1_repeat_cycle 0x2c dout_start _dly [15:8] dout_start[15:8] 0x0003 r a a w e e [7:0] dout_start[7:0] 0x2d dout_config [15:8] reserved[9:2] 0x00 r a a w e e [7:0] r eserved[1:0] dout_val dout_mode dout_stop 0x2e dac4_cst [15:8] dac4_const[11:4] 0x0 0 r a a w e e [7:0] dac4_const[3:0] reserved 0x2f dac3_cst [15:8] dac3_const[11:4] 0x00 r a a w e e [7:0] dac3_const[3:0] reserved 0x30 dac2_cst [15:8] dac2_const[11:4] 0x00 r a a w e e [7:0] dac2_const[3:0] reserved 0x31 dac1_cst [15:8] dac1_const[11:4] 0x00 r a a w e e [7:0] dac1_const[3:0] reserved 0x32 dac4_dgain [15:8] dac4_dig_gain[11:4] 0x0 0 r a a w e e [7:0] dac4_dig_gain[3:0] reserved 0x33 dac3_dgain [15:8] dac3_dig_gain[11:4] 0x0 0 r a a w e e [7:0] dac3_dig_gain[3:0] reserved 0x34 dac2_dgain [15:8] dac2_dig_gain[11:4] 0x0 0 r a a w e e [7:0] dac2_dig_ gain[3:0] reserved 0x35 dac1_dgain [15:8] dac1_dig_gain[11:4] 0x0 0 r a a w e e [7:0] dac1_dig_gain[3:0] reserved 0x36 saw4_3config [15:8] saw_step4 saw_type4 0x0 0 r a a w e e [7:0] saw_step3 saw_type3 0x37 saw2_1config [15:8] saw_step2 saw_type2 0x0 0 r a a w e e [7:0] saw_step1 saw_type1 0x38 to 0x3d reserved reserved 0x3e dds_tw32 [15:8] ddstw_msb[15:8] 0x0 0 r a a w e e [7:0] ddstw_msb[7:0] 0x3f dds_tw1 [15:8] ddstw_lsb 0x0 0 r a a w e e [7:0] reserved 0 x 40 dds4_pw [15:8] dds4_phase[15:8] 0x00 r a a w e e [7:0] dds4_phase[7:0] 0x41 dds3_pw [15:8] dds3_phase[15:8] 0x0 0 r a a w e e [7:0] dds3_phase[7:0] 0x42 dds2_pw [15:8] dds2_phase[15:8] 0x00 r a a w e e [7:0] dds2_phase[7:0] 0x43 dds1_pw [15:8] dds1_phase[15:8] 0x0 0 r a a w e e [7:0] dds1_phase[7:0] 0x44 trig_tw_sel [15:8] reserved[13:6] 0x0 0 r a a w e e [7:0] reserved[5:0] trig_delay_en reserved 0x45 ddsx_config [15:8] dds_cos_en4 dds_msb_en4 reserved dds_cos_en3 dds_msb_en3 reserved 0x00 r a a w e e [7:0] dds_cos_en2 dds_msb_en2 reserved dds_cos_en1 dds_msb_en1 reserved tw_mem_en 0x47 tw_ram _config [15:8] reserved r eserved 0x00 r a a w e e [7:0] reserved tw_mem_shift AD9106 data sheet rev. a | page 32 of 48 addr (hex) register name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r a a w e e 0x50 start_dly4 [15:8] start_delay4[15:8] 0x00 r a a w e e [7:0] start_delay4[7:0] 0x51 start_addr4 [15:8] start_addr4[11:4] 0x0 0 r a a w e e [7:0] start_a ddr4[3:0] reserved 0x52 stop_addr4 [15:8] stop_addr4[11:4] 0x00 r a a w e e [7:0] stop_addr4[3:0] reserved 0x53 dds_cyc4 [15:8] dds_cyc4[15:8] 0x0001 r a a w e e [7:0] dds_cyc4[7:0] 0x54 start_dly3 [15:8] start_delay3[1 5:8] 0x00 r a a w e e [7:0] start_delay3[7:0] 0x55 start_addr3 [15:8] start_addr3[11:4] 0x0 0 r a a w e e [7:0] start_addr3[3:0] reserved 0x56 stop_addr3 [15:8] stop_addr3[11:4] 0x0 0 r a a w e e [7:0] stop_add r3[3:0] reserved 0x57 dds_cyc3 [15:8] dds_cyc3[15:8] 0x0001 r a a w e e [7:0] dds_cyc3[7:0] 0058 start_dly2 [15:8] start_delay2[15:8] 0x0 0 r a a w e e [7:0] start_delay2[7:0] 0x59 start_addr2 [15:8] start_addr2[11:4] 0x00 r a a w e e [7:0] start_addr2[3:0] reserved 0x5a stop_addr2 [15:8] stop_addr2[11:4] 0x00 r a a w e e [7:0] stop_addr2[3:0] reserved 0x5b dds_cyc2 [15:8] dds_cyc2[15:8] 0x0001 r a a w e e [7:0] dds_cyc2[7:0 ] 0x5c start_dly1 [15:8] start_delay1[15:8] 0x00 r a a w e e [7:0] start_delay1[7:0] 0x5d start_addr1 [15:8] start_addr1[11:4] 0x00 r a a w e e [7:0] start_addr1[3:0] reserved 0x5e stop_addr1 [15:8] stop_addr1[11:4] 0x0 0 r a a w e e [7:0] stop_addr1[3:0] reserved 005f dds_cyc1 [15:8] dds_cyc1[15:8] 0x0001 r a a w e e [7:0] dds_cyc1[7:0] 0060 cfg_error [15:8] error_clear cfg_error[8:2] 0x0 0 r [7:0] cfg_error[1:0] dout_start_lg _err pat_dly_short _err dout_start _short_err period _short_err odd_addr _err mem_read _err 0x6000 to 0x6fff sram _ data [15:8] reserved sram_data[11:8] n/a r a a w e e [7:0] sram_data [7:0] data sheet AD9106 rev. a | page 33 of 48 register description s spi control register (spiconfig , address 0x 00 ) table 15 . bit descriptions for spiconfig bits bit field name settings description reset access 15 lsbfirst lsb first selection . 0 r a a w e e 0 msb first per spi standard (default) . 1 lsb first per spi standard . 14 spi3wire selects if spi is using 3 - wire or 4 - wire interface. 0 r a a w e e 0 4-w ire spi . 1 3-w ire spi . 13 reset executes software reset of spi and controllers, reloads default register values, except for register 0x00. 0 r a a w e e 0 normal status . 1 reset s whole register map, except for register 0x 00 . 12 doublespi doub l e spi data line. 0 r a a w e e 0 the spi port has only 1 data line and can be used as a 3 - wire or 4 - wire interface . 1 the sp i port has 2 data lines: both bidirectional defining a pseudo dual 3- wire interface where a a cs e e aa a nd sclk are shared between the two ports. this mode is only available for ram data read or write . 11 spi_drv double - drive ability for spi output. 0 r a a w e e 0 single spi output drive ability . 1 two - time drive ability on spi output . 10 dout_en 0 1 enable s dout signal on sdo/sdi2/dout pin. sdo/sdi2 function input/output . dout function output . 0 r a a w e e [9:6] reserved r a a w e e 5 dout_enm 0f 1 enable dout signal on sdo/sdi2/dout pin. r a a w e e 4 spi_drvm 1 double - drive ability for spi output. 0 r a a w e e 3 doublespim 1 doub l e spi data line. 0 r a a w e e 2 resetm 1 executes software reset of spi and controllers, reloads default register values , except for register 0x00. 0 r a a w e e 1 spi3wirem 1 selects if spi is using 3 - wire or 4 - wire interface. 0 rw 0 lsbfirstm 1 lsb first selection . 0 r a a w e e 1 spiconfig[10:15] should always be set to the mirror of spiconfig[5:0] to allow easy recovery of the spi ope ration when the lsbfirst bit is set incorrectly. bit[15] = bit[0], bit[14] = bit[1], bit[13] = bit[2], bit[12] = bit[3], bit[11] = bit[4] and bit[10] = bit[5] . AD9106 data sheet rev. a | page 34 of 48 power status register (powerconfig , address 0 x 01) table 16 . bit descriptions for powerconfig bits bit field name settings description reset access [15:12] reserved 0x0 0 r a a w e e 11 clk_ldo_stat read -o nly flag indicating clkvdd_1p8 ldo is on. 0 r 10 dig1_ldo_stat read -o nly flag indicating dvdd1 ldo is on. 0 r 9 dig2_ldo_stat read -o nly flag indicating dvdd2 ldo is on. 0 r 8 pdn_ldo_clk disable s the clkvdd_1p8 ldo. an external supply is req uired. 0 r a a w e e 7 pdn_ldo_dig1 disable s the dvdd1 ldo. an external supply is required. 0 r a a w e e 6 pdn_ldo_dig2 disable s the dvdd2 ldo. an external supply is required. 0 r a a w e e 5 ref_pdn disable s 10 k? r esistor that creates refio voltage. user can drive with external voltage or provide external bg resistor. 0 r a a w e e 4 ref_ext power down main bg reference including dac bias. 0 r a a w e e 3 dac1_sleep disable s dac1 output cur rent. 0 r a a w e e 2 dac2_sleep disable s dac2 output current. 0 r a a w e e 1 dac3_sleep disable s dac3 output current. 0 r a a w e e 0 dac4_sleep disable s dac4 output current. 0 r a a w e e clock control register (clockconfig , address 0 x 02) table 17 . bit descriptions for clockconfig bits bit field name settings description reset access [15:12] reserved 0x0 00 r a a w e e 11 dis_clk1 disable s the analog clock to dac1 out of the clock distribution block. 0 r a a w e e 10 dis_clk2 disable s the analog clock to dac2 out of the clock distribution block. 0 r a a w e e 9 dis_clk3 disable s the analog clock to dac3 out of the clock distribution block. 0 r a a w e e 8 dis_clk4 disable s the analog clock to dac4 out of the clock distribution block. 0 r a a w e e 7 dis_dclk disable s the clock to core digital block. 0 r a a w e e 6 clk_sleep enables a very low power clock mode. 0 r a a w e e 5 clk_pdn disables and powers down main clock receiver. no clocks will be active in the part. 0 r a a w e e 4 eps enable s power save (eps) enables a low power option for the clock receiver , but maintains low jitter performance on dac clock rising edge. the dac clock falling edge is substantially degraded. 0 r a a w e e 3 dac1_inv_clk cannot use eps while using this bit . inverts the clock inside dac c ore 1 allowing 180 ph ase shift in dac1 update t iming. 0 r a a w e e 2 dac2_inv_clk cannot use eps while using this bit . inverts the clock inside dac c ore 2 allowing 180 ph ase shift in dac2 update timing. 0 r a a w e e 1 dac3_inv_clk cannot use eps while using this bit . invert s the clock inside dac c ore 3 allowing 180 ph ase shift in dac3 update timing. 0 r a a w e e 0 dac4_inv_clk cannot use eps while using this bit . inverts the clock inside dac c ore 4 allowing 180 ph ase shift in dac4 update timing. 0 r a a w e e reference resistor register (refadj , address 0 x 03) table 18 . bit descriptions for refadj bits bit field name settings description reset access [15:6] reserved 0x000 r a a w e e [5:0] bgdr adjusts the bg 10 k? resistor (nominal) to 8 k? to 12 k?, c hanges bg voltage from 800 mv to 1.2 v, respectively. 0x00 r a a w e e data sheet AD9106 rev. a | page 35 of 48 dac4 analog gain register (dac4again , ad dress 0 x 04) table 19 . bit descriptions for dac4again bits bit field name settings description reset access 15 reserved 0 r a a w e e [14:8] dac4_gain_cal dac4 analog gain calibration output read only. 0x00 r 7 reserved 0 r a a w e e [6:0] dac4_gain dac4 analog gain control while not in calibration mode twos complement. 0x00 r a a w e e dac3 analog gain register (dac3again , address 0 x 05) table 20. bit descriptions for dac3again bits bit field name settings description reset access 15 reserved 0 r a a w e e [14:8] dac3_gain_cal dac3 analog gain calibration output read only. 0x00 r 7 reserved 0 r a a w e e [6:0] dac3_gain dac3 analog gain control while not in calibration mode twos complement. 0x00 r a a w e e dac2 an alog gain register (dac2again , address 0 x 06) table 21. bit descriptions for d ac2again bits bit field name settings description reset access 15 reserved 0 r a a w e e [14:8] dac2_gain_cal dac2 analog gain calibration out put read only. 0x00 r 7 reserved 0 r a a w e e [6:0] dac2_gain dac2 analog gain control while not in calibration mode twos complement. 0x00 r a a w e e dac1 analog gain register (dac1again , address 0 x 07) table 22. bit descriptions for dac1again bits bit field name settings description reset access 15 reserved 0 r a a w e e [14:8] dac1_gain_cal dac1 analog gain calibration output read only . 0x00 r 7 reserved 0 r a a w e e [6:0] dac1_gain dac1 analog gain control while not in calibration mode twos complement. 0x00 r a a w e e dac analog gain range register (dacxrange , address 0 x 08) table 23. bit descriptions for dacxrange bits bit field name se ttings description reset access [15:8] reserved 0x00 r a a w e e [7:6] dac4_gain_rng dac4 gain range control. 0x0 r a a w e e [5:4] dac3_gain_rng dac3 gain range control. 0x0 r a a w e e [3:2] dac2_gain_rng dac2 ga in range control. 0x0 r a a w e e [1:0] dac1_gain_rng dac1 gain range control. 0x0 rw AD9106 data sheet rev. a | page 36 of 48 fsadj4 register (dac4rset , address 0 x0 9) table 24 . bit descriptions for dac4rset bits bit field name settings description reset acces s 15 dac4_rset_en for write, e nable the internal r set resistor for dac 4; f or read, r set for dac 4 is enabled during calibration mode. 0x0 0 r a a w e e [14:13] reserved 0x0 0 r a a w e e [12:8] dac4_rset_cal digital control value of r set resistor for dac 4 after calibration read only. 0x00 r [7:5] reserved 0x0 0 r a a w e e [4:0] dac4_rset digital control to set the value of r set resistor in dac 4. 0x0a r a a w e e fsadj3 register (dac3rset , address 0 x 0a) table 25 . bit descriptions for dac3rset bits bit field name settings description reset access 15 dac3_rset_en for write, e nable the internal r set resistor for dac3; f or read, r set for dac 3 is enabled during calibration mode. 0 r a a w e e [14:13] reserved 0x0 r a a w e e [12:8] dac3_rset_cal digital control value of r set resistor for dac 3 after calibration read only. 0x00 r [7:5] reserved 0x0 r a a w e e [4:0] dac3_rset digital control to set the value of r set resistor in dac 3. 0x0a r a a w e e fsadj2 register (dac2rset , address 0x 0b) table 26 . bit descriptions for dac2rset bits bit field name settings description reset access 15 dac2_rset_en for write, enable the internal r set resistor for dac2; for read, r set for dac2 is enabled during calibration mode. 0 r a a w e e [14:13] reserved 0x0 r a a w e e [12:8] dac2_rset_cal digital control value of r set resistor for dac2 after ca libration read only. 0x00 r [7:5] reserved 0x0 r a a w e e [4:0] dac2_rset digital control to set the value of r set resistor in dac2. 0xa r a a w e e fsadj1 register (dac1rset , address 0x 0c) table 27 . bit descriptions for dac1rset bits bit field name settings description reset access 15 dac1_rset_en for write, e nable the internal r set resistor for dac1; f or read, r set for dac1 is enabled during calibration mode. 0x00 r a a w e e [14:13] reserved 0x00 r a a w e e [12:8] dac1_rset_cal digital control value of r set resistor for dac 1 after calibration read only. 0x00 r [7:5] reserved 0x0 r a a w e e [4:0] dac1_rset digital control to set the value of r set resistor in dac 1. 0x0a r a a w e e data sheet AD9106 rev. a | page 37 of 48 calibration register (calconfig , address 0x 0d) table 28 . bit descriptions for calconfig bits bit field name settings description reset access 15 reserved 0 r a a w e e 14 comp_offset_ of compensation offset calibration value overflow. 0 r 13 comp_offset_uf compensation offset calibration value underflow. 0 r 12 rset_cal_of r set calibration value overflow. 0 r 11 rset_cal_uf r set calibration value underflow. 0 r 10 gain_cal_of g ain calibration value overflow. 0 r 9 gain_cal_uf gain calibration value underflow. 0 r 8 cal_reset pulse this bit high and low to reset the calibration results. 0 r a a w e e 7 1 cal_mode read -o nly flag indicating calibration is being used . 0 r 6 1 cal_mode_en enables the gain calibration circuitry. 0 r a a w e e [5:4] comp_cal_rng offset calibration range . 0x0 r a a w e e 3 cal_clk_en enables the calibration clock to calibration circuitry. 0 r a a w e e [2:0] cal_clk_div sets divider from dac clock to calibration clock. 0x0 r a a w e e 1 change of location co mp offset register (compoffset , address 0x0 e) table 29 . bit descriptions for compoffset bits bit field name s ettings description reset access 15 reserved 0x0 0 r a a w e e [14:8] comp_offset_cal the result of the offset calibration for the comparator . 0x00 r [7:2] reserved 0x00 r a a w e e 1 cal_fin read -o nly flag indicating calibra tion is completed. 0x0 0 r 0 start_cal start a calibration cycle. 0x0 0 r a a w e e update pattern register (ramupdate , address 0x1 d) table 30 . bit descriptions for ramupdate bits bit name settings description reset acces s [15:1] reserved 0x00 r a a w e e 0 ramp update update all spi setting with new configuration ( self clearing ). 0 r a a w e e command/status register (pat_status , address 0x 1e) table 31 . bit descriptions fo r pat_status bits bit field name settings description reset access [15:4] reserved 0x000 r a a w e e 3 buf_read read back from updated buffer. 0 r a a w e e 2 mem_access memory spi access enable. 0 r a a w e e 1 pat tern s tatus of pattern being played, read o nly. 0 r 0 run allows the pattern generation and stop pattern after trigger. 0 r a a w e e AD9106 data sheet rev. a | page 38 of 48 co mmand/status register (pat_type , address 0x 1f) table 32 . bit descriptions for pat _type bits bit field name settings description reset access [15:1] reserved 0x0000 r a a w e e 0 pattern_rpt setting this bit allows the pattern to repeat the number of times defined in dac4_3patx and dac2_1patx . 0 r a a w e e 0 pattern continuously run s. 1 pattern repeat s the number of times defined in dac4_3patx and dac2_1patx. trigger start to real pattern delay register (pattern_dl y , address 0x 20) table 33. bit descriptions for pattern_dl y bit s bit field name settings description reset access [15:0] pattern_delay time between trigger low and pattern start in number of dac clock cycles + 1. 0x000e r a a w e e dac4 d igital offset register (dac4dof , address 0x 22) table 34 . bit descriptions for dac4dof bits bit field name settings description reset access [15:4] dac4_dig_offset dac4 digital offset. 0x000 r a a w e e [3:0] reserved 0x0 0 r a a w e e dac3 digital offset register (dac3do f , address 0x 23) table 35 . bit descriptions for dac3dof bits bit field name settings description reset access [15:4] dac3_dig_offset dac3 digital offset. 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e da c2 digital offset register (dac2dof , address 0x 24) table 36 . bit descriptions for dac2dof bits bit field name settings description reset access [15:4] dac2_dig_offset dac2 digital offset. 0x000 r a a w e e [3:0] reserved 0x0 0 r a a w e e dac1 digital offset register (dac1dof , address 0x 25) table 37 . bit descriptions for dac1dof bits bit field name settings description reset access [15:4] dac1_dig_offset dac1 digital offset. 0x000 r a a w e e [3:0] reserved 0x0 0 r a a w e e data sheet AD9106 rev. a | page 39 of 48 wave3/ wave 4 select register (wav4_3config , address 0x 26) table 38 . bit descriptions for wav4_3config bits bit field name settings description reset access [15:14] re served 0x0 0 r a a w e e [13:12] prestore_sel4 0x0 0 r a a w e e 0 constant value held into dac4 c onstant value msb/lsb register . 1 saw tooth defined in dac4 saw tooth config uration register (saw4_3config). 2 pseudo - ran dom sequence . 3 dds4 output . [11:10] reserved 0x0 0 r a a w e e [9:8] wave_sel4 0x1 r a a w e e 0 waveform read from ram between start_addr4 and stop_addr4. 1 pre stored waveform . 2 pre stored waveform using st art_delay4 and pattern_period . 3 prestored waveform modulated by waveform from ram . [7:6] reserved 0x0 0 r a a w e e [5:4] prestore_sel3 0x0 0 r a a w e e 0 constant value held into dac3 c onstant value msb/lsb register . 1 saw tooth de fined in dac3 saw tooth config uration register (saw4_3config). 2 pseudo - random sequence . 3 dds3 output . [3:2] reserved 0x0 0 r a a w e e [1:0] wave_sel3 0x1 rw 0 waveform read from ram between start_addr3 and stop_addr3. 1 pre stored waveform . 2 pre stored waveform using start_delay3 and pattern_period . 3 pr e stored waveform modulated by waveform from ram . wave1/ wave 2 select register (wav2_1config , address 0x 27) table 39. bit descriptions for wav2_1config bits bit field name settings description reset access [15:14] reserved 0x0 r a a w e e [13:12] prestore_sel2 0x0 r a a w e e 0 constant value held into dac2 c onstant value msb/lsb register . 1 saw tooth defined in dac2 sawt ooth config uration register (saw2_1config ). 2 pseudo - random sequence . 3 dds2 output . 11 mask_dac4 mask dac4 to dac4_const value. 0 r a a w e e 10 ch2_add add dac2 and dac4, output at dac2. 0 r a a w e e 0 normal operation for dac2/ dac 4. 1 add dac2 and dac4, output from dac2 . [9:8] wave_sel2 0x1 r a a w e e 0 waveform read from ram between start_addr2 and stop_addr2. 1 pre stored waveform . 2 pre stor ed waveform using start_delay2 and pattern_period . 3 pre stored waveform modulated by w aveform from ram . [7:6] reserved 0x0 r a a w e e AD9106 data sheet rev. a | page 40 of 48 bits bit field name settings description reset access [5:4] prestore_sel1 0x0 r a a w e e 0 constant value held into dac1 c onstant value msb/lsb register . 1 saw tooth defined in dac1 saw tooth config uration register (saw2_1config ). 2 pseudo - random sequence . 3 dds1 output . 3 mask_dac3 mask dac3 to dac3_const value. 0 r a a w e e 2 ch1_add add dac1 and dac3, output at dac1. 0 r a a w e e 0 normal operation for dac1/ dac 3. 1 add dac1 and dac3, and output at dac1. in th is start_delay case, dac3 output remains unchanged . [1:0] wave_sel1 0x1 r a a w e e 0 waveform read from ram bet ween start_addr1 and stop_addr1. 1 pre stored waveform . 2 pre stored waveform using start_delay1 and pattern_period . 3 pre stored waveform modulated by waveform from ram . dac time control register (pat_time base , ad dress 0x 28) table 40 bit descriptions for pat_timebase bits bit field name settings description reset access [15:12] reserved 0x0 0 r a a w e e [11:8] hold number of times the dac value holds the sample (0 = dac holds for 1 sample). 0x1 r a a w e e [7:4] pat_period_base number of dac clock period per pattern_period lsb (0 = pattern_period lsb = 1 dac clock period) . 0x1 r a a w e e [3:0] start_delay_base number of dac clock period per start_delayx lsb (0 = start_delayx lsb = 1 dac clock period) . 0x1 r a a w e e pattern period register (pat_period , address 0x0 29) table 41 bit descriptions for pat_period bits bit field name settings description reset access [15:0] pattern_period patte rn period register . 0x8000 r a a w e e dac3/ dac 4 pattern repeat cycles register (dac4_3patx , address 0x 2a) table 42 bit descriptions for dac4_3patx bits bit field name settings description reset access [15:8] dac4_repea t_cycle number of dac4 pattern repeat cycles + 1 , (0 ? r epeat 1 pattern) . 0x01 r a a w e e [7:0] dac3_repeat_cycle number of dac3 pattern repeat cycles + 1 , (0 ? r epeat 1 pattern) . 0x01 r a a w e e dac1/ dac 2 pattern rep eat cycles register ( dac2_1patx, address 0x 2b) table 43 bit descriptions for dac2_1patx bits bit field name settings description reset access [15:8] dac2_repeat_cycle number of dac2 pattern repeat cycles + 1, (0 ? r epeat 1 pattern) . 0x01 r a a w e e [7:0] dac1_repeat_cycle number of dac1 pattern repeat cycles + 1, (0 ? r epeat 1 pattern) . 0x01 r a a w e e data sheet AD9106 rev. a | page 41 of 48 trigger s tart to dout s ignal register (dout_start _dly , address 0x 2c ) table 44 . bit descripti ons for dout_start _dly bits bit field name settings description reset access [15:0] dout_start time between trigger low and dout signal high in number of dac clock cycles . 0x0003 r a a w e e dout config register (dout_config , address 0x 2d) table 45 . bit descriptions for dout_config bits bit field name settings description reset access [15:6] reserved 0x0000 r a a w e e 5 dout_val manually set s dout signal value, only valid when dout_mode = 0 (manual mode ). 0 r a a w e e 4 dout_mode set s different enable signal mode. 0 r a a w e e 0x0 dout pin is output from sdo/sdi2/dout pin and is manually controlled by b it 5, dout_en in register 0x00 which must be set to use this feature. 0x1 dout pin is output from sdo/sdi2/dout. the pin is controlled by dout_start and dout_stop. dout_en in register 0x00 must be set to use this feature. [3:0] dout_stop time between p attern end and dout signal low in number of dac clock cycles. 0x0 r a a w e e dac4 co nstant v alue register (dac4_cst , address 0x 2e) table 46 . bit descriptions for dac4_cst bits bit field name settings description reset access [15:4] dac4_const most significant b yte of dac4 constant value . 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e dac3 co nstant v alue register (dac3_cst , address 0x 2f) table 47 . bit descriptions for dac3_cst bits bit field name settings description reset access [15:4] dac3_const most significant b yte of dac3 constant value. 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e dac2 constant v alue register (dac2_cst , address 0x 30) table 48 . bit descriptions for dac2_cst bits b it field name settings description reset access [15:4] dac2_const most signific ant b yte of dac2 constant value. 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e dac1 constant v alue register (dac1_cst , address 0x 31) table 49 . bit descriptions for dac1_cst bits bit field name settings description reset access [15:4] dac1_const most signific ant b yte of dac1 constant value. 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e AD9106 data sheet rev. a | page 42 of 48 dac4 digita l gain register (dac4_dgain , address 0x32 ) table 50 . bit descriptions for dac4_dgain bits bit field name settings description reset access [15:4] dac4_dig_gain dac4 digital gain r ange of +2 to ?2. 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e dac3 digital gain register (dac3_dgain , address 0x 33) table 51 . bit descriptions for dac3_dgain bits bit field name settings description reset access [15:4] dac3_dig_gain dac3 digital gain. ra nge of +2 to ?2. 0x00 0 r a a w e e [3:0] reserved 0x0 r a a w e e dac2 digital gain register (dac2_dgain , address 0x 34) table 52 . bit descriptions for dac2_dgain bits bit field name settings description reset acces s [15:4] dac2_dig_gain dac2 digital gain. range of +2 to ?2. 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e dac1 digital gain register (dac1_dgain , address 0x 35) table 53 . bit descriptions for dac1_dgain bits bit field name settings description reset access [15:4] dac1_dig_gain dac1 digital gain. range of +2 to ?2. 0x000 r a a w e e [3:0] reserved 0x0 r a a w e e dac3/4 sawtooth c onfig uration register (saw4_3config , address 0x 36) table 54 . bit descriptions for saw4_3config bits bit field name settings description reset access [15:10] saw_step4 number of samples per step for dac4. 0x01 r a a w e e [9:8] saw_type4 the type of sawtooth (positiv e, negative , or triangle) for dac4. 0x0 r a a w e e 0 ramp up saw wave . 1 ramp down saw wave . 2 triangle saw wave . 3 no wave, zero . [7:2] saw_step3 number of samples per step for dac3. 0x01 r a a w e e [1:0] saw _type3 the type of sawtooth (positive, negative , or triangle) for dac3. 0x0 r a a w e e 0 ramp up saw wave . 1 ramp down saw wave . 2 triangle saw wave . 3 no wave, zero . dac1/2 sawtooth configuration register (saw2_1config , address 0x 37) table 55 . bit descriptions for saw2_1config bits bit field name settings description reset access [15:10] saw_step2 number of samples per step for dac2. 0x01 r a a w e e [9:8] saw_type2 the type of sawtooth (positive, negative , or triangle) for dac2. 0x0 r a a w e e 0 ramp up saw wave . 1 ramp down saw wave . 2 triangle saw wave . 3 no wave, zero . data sheet AD9106 rev. a | page 43 of 48 bits bit field name settings description reset access [7:2] saw_step1 number of samples per step for dac1. 0x01 r a a w e e [1:0] saw_type1 the type of sawtooth (positive, negative , or triangle) for dac1. 0x0 r a a w e e 0 ramp up saw wave . 1 ramp down saw wave . 2 triangle saw wave . 3 no wave, zero . dds tuning w ord msb register (dds_tw32 , address 0x 3e) table 56 . bit descriptions for dds_tw32 bits bit field name settings description reset access [15:0] ddstw_msb dds t uning word msb. 0x0000 r a a w e e dds tuning word lsb register (dds_tw1 , address 0x 3f) table 57 . bit descriptions for dds_tw1 bits bit field name settings description reset access [15:8] ddstw_lsb dds t uning word lsb. 0x00 r a a w e e [7:0] reserved 0x00 r a a w e e dds4 phase offset register (dds 4_pw , address 0x 40) table 58 . bit descriptions for dds4_pw bits bit field name settings description reset access [15:0] dds4_phase dds4 phase offset . 0x0000 r a a w e e dds3 phase offset register (dds3_pw , address 0x 41) table 59 . bit descriptions for dds3_pw bits bit field name settings description reset access [15:0] dds3_phase dds3 phase offset . 0x0000 r a a w e e dds2 phase offset register (dds2_pw , address 0x 42) table 60 . bit descriptions for dds2_pw bits bit field name settings description reset access [15:0] dds2_phase dds2 phase offset . 0x0000 r a a w e e dds1 phase offset register (dds1_pw , address 0x 43) table 61 . bit d escriptions for dds1_pw bits bit field name settings description reset access [15:0] dds1_phase dds1 phase offset. 0x0000 r a a w e e AD9106 data sheet rev. a | page 44 of 48 pattern control 1 register (trig_tw_sel , address 0 x 44) table 62 . bit descriptions fo r trig_tw_sel bits bit field name settings description reset access [15:2] reserved 0x0000 r a a w e e 1 trig_delay_en enable start delay as trigger delay for all four channels. 0 r a a w e e 0 delay repeats for all patterns . 1 delay is only at the start of first pattern . 0 reserved 0 r a a w e e pattern control 2 register (ddsx_config , address 0x 45) table 63 . bit descriptions for ddsx_config bits bit field name settings description reset access 15 dds_cos_en4 enable dds4 cosine output of dds instead of s ine wave. 0 r a a w e e 14 dds_msb_en4 enable the clock for the ram address. increment is coming from the dds4 msb. default is coming from dac clock. 0 r a a w e e 13 reserved 0 r a a w e e 12 reserved 0 r a a w e e 11 dds_cos_en3 enable dds3 c osine output of dds instead of s ine wave. 0 r a a w e e 10 dds_msb_en3 enable the clock for the ram address. i ncrement is comi ng from the dds3 msb. default is coming from dac clock. 0 r a a w e e 9 phase_mem_en3 enable dds3 phase offset input coming from ram reading start_addr3. since phase word is 8 bit s and ram data is 14 bit s , only 8 msb of ram are taken into account. default is coming from spi map, dds3_phase. 0 r a a w e e 8 reserved 0 r a a w e e 7 dds_cos_en2 enable dds2 c osine output of dds instead of s ine wave. 0 r a a w e e 6 dds_msb_en2 enabl e the clock for the ram a ddress. i ncrement is coming from the dds2 msb. default is coming from dac clock. 0 r a a w e e 5 reserved 0 r a a w e e 4 reserved 0 r a a w e e 3 dds_cos_en1 enable dds1 c osine output of dds instead of s ine wave. 0 r a a w e 2 dds_msb_en1 enable the clock for the ram address. increment is coming from the dds1 msb. default is coming from dac clock. 0 r a w e 1 reserved 0 r a w e 0 tw_mem_en enable dds tuning word input coming from ram reading using start_addr1. since tuning word is 24 bit s and ram data is 14 bit s, 10 bits are set to 0s depending on the value of the tw_mem_shift bits in the tw_ram_config register. default is coming from spi map, ddstw. 0 r a w e tw_ram_config register ( tw_ram _config , address 0x 47 ) table 64. bit descriptions for tw_ram_config bits bit field name settings description reset access [15:5] reserved 0x0 00 r a w e [4:0] tw_mem_shift tw_mem_ en1 must be set = 1 to use this bit field . 0x00 r a w e 0x00 dds1tw = {ram[11:0],12'b0} 0x01 dds1tw = {dds1tw[23],ram[11:0],11'b0} 0x02 dds1tw = {dds1tw[23:22],ram[11:0],10'b0} 0x03 dds1tw = {dds1tw[23:21],ram[11:0],9'b0} 0 x04 dds1tw = {dds1tw[23:20],ram[11:0],8'b0} 0x05 dds1tw = {dds1tw[23:19],ram[11:0],7'b0} 0x06 dds1tw = {dds1tw[23:18],ram[11:0],6'b0} data sheet AD9106 rev. a | page 45 of 48 bits bit field name settings description reset access 0x07 dds1tw = {dds1tw[23:17],ram[11:0],5'b0} 0x08 dds1tw = {dds1tw[23:16],ram[11:0],3'b0} 0x09 dd s1tw = {dds1tw[23:15],ram[11:0],4'b0} 0x0a dds1tw = {dds1tw[23:14],ram[11:0],2b0} 0x0b dds1tw = {dds1tw[23:13],ram[11:0],1b0} 0x0c dds1tw = {dds1tw[23:12],ram[11:0]} 0x0d dds1tw = {dds1tw[23:11],ram[11:1]} 0x0e dds1tw = {dds1tw[2 3:10],ram[11:2]} 0x0f dds1tw = {dds1tw[23:9],ram[11:3]} 0x10 dds1tw = {dds1tw[23:8],ram[11:4]} x reserved start delay4 register (start_dly4 , address 0x 50) table 65 . bit descriptions for start_dly4 bits bit field name settings description reset access [15:0] start_delay4 start delay of dac4. 0x0 000 r a w e start address4 register (start_addr4 , address 0x 51) table 66 . bit descriptions for start_addr4 bits bit field name settings de scription reset access [15:4] start_addr4 ram address where dac4 starts to read w aveform. 0x000 r a w e [3:0] reserved 0x0 0 r a w e stop address4 register (stop_addr4 , address 0x 52) table 67 . bit descriptions for stop_addr4 bits bit field name settings description reset access [15:4] stop_addr4 ram address where dac4 stops to read w aveform. 0x000 r a w e [3:0] reserved 0x0 0 r a w e dds cycle 4 register (dds_cyc 4 , address 0x 53) table 68 . bit descriptions for dds_cyc4 bits bit field name settings description reset access [15:0] dds_cyc4 number of sine wave cycles when dds prestored waveform with start and stop delays is selected for dac4 ou tput. 0x0001 r a w e start delay3 register (start_dly3 , address 0x 54) table 69 . bit descriptions for start_dly3 bits bit field name settings description reset access [15:0] start_delay3 start delay of dac3. 0x0 000 r a w e start address3 register (start_addr3 , address 0x 55) table 70 . bit descriptions for start_addr3 bits bit field name settings description reset access [15:4] start_addr3 ram address where dac3 starts to read w avefo rm. 0x000 r a w e [3:0] reserved 0x0 r a w e AD9106 data sheet rev. a | page 46 of 48 stop address3 register (stop_addr3 , address 0x 56) table 71 . bit descriptions for stop_addr3 bits bit field name settings description reset access [15:4] stop_ addr3 ram address where dac3 stops to read w aveform. 0x0000 r a w e [3:0] reserved 0x0 r a w e dds cycles3 register (dds_cyc3 , address 0x 57) table 72 . bit descriptions for dds_cyc3 bits bit field name s ettings description reset access [15:0] dds_cyc3 number of sine wave cycles when dds pre stored waveform with start and stop delays is selected for dac3 output. 0x0001 r a w e start delay2 register (start_dly2 , address 0x 58) table 73 . bit descriptions for start_dly2 bits bit field name settings description reset access [15:0] start_delay2 start delay of dac2. 0x0 000 r a w e start address2 register (start_addr2 , address 0x 59) table 74 . bit descriptions for start_addr2 bits bit field name settings description reset access [15:4] start_addr2 ram address where dac2 starts to read w aveform. 0x000 r a w e [3:0] reserved 0x0 r a w e stop address2 register ( stop_addr2 , address 0x 5a) table 75 . bit descriptions for stop_addr2 bits bit field name settings description reset access [15:4] stop_addr2 ram address where dac2 stops to read w aveform. 0x000 r a w e [3:0] reserved 0x0 r a w e dds cycle 2 register (dds_cyc2 , address 0x 5b) table 76 . bit descriptions for dds_cyc2 bits bit field name settings description reset access [15:0] dds_cyc2 number of sine wave cycles when dds pre stored wave form with start and stop delays is selected for dac2 output. 0x0001 r a w e start delay1 register (start_dly1 , address 0x 5c) table 77 . bit descriptions for start_dly1 bits bit field name settings description reset acces s [15:0] start_delay1 start delay of dac1. 0x00 00 r a w e data sheet AD9106 rev. a | page 47 of 48 start address1 register (start_addr1 , address 0x 5d) table 78 . bit descriptions for start_addr1 bits bit field name settings description reset access [15:4] st art_addr1 ram address where dac1 starts to read w aveform. 0x000 r a w e [3:0] reserved 0x0 r a w e stop address1 register ( stop_addr1 , address 0x 5e ) table 79 . bit descriptions for stop_addr1 bits bit fi eld name settings description reset access [15:4] stop_addr1 ram ad dress where dac1 stops to read w aveform. 0x0 00 r a w e [3:0] reserved 0x0 r a w e dds cycle1 register ( dds_cyc1 , address 0x 5f ) table 80 . bit descriptions for dds_cyc1 bits bit field name settings description reset access [15:0] dds_cyc1 number of sine wave cycles when dds prestored waveform with start and stop delays is selected for dac1 output. 0x0001 r a w e cfg error register (c fg_error, address 0x 60 ) table 81 . bit descriptions for cfg_error bits bit field name settings description reset access 15 error_clear writ ing this bit clear s all errors. 0 r [14:6] cfg_error 0x0 0 r 5 dout_ start_lg_err when dout_start is larger than pattern delay, this error is toggled. 0 r 4 pat_dly_short_err when pattern delay value is smaller than default value, this error is toggled. 0 r 3 dout_start_short_err when dout_start value is smaller than default value , this error is toggled. 0 r 2 period_short_err when p eriod register setting value is smaller than pattern play cycle, this error is toggled. 0 r 1 odd_addr_err when memory pattern play is not even in length in trigger delay mode, this error flag is to ggled. 0 r 0 mem_read_err when there is a memory read conflict, this error flag is toggled. 0 r AD9106 data sheet rev. a | page 48 of 48 outline dimensions 08-16-2010-b 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad pin 1 indicator seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220-whhd-5 with exception to exposed pad dimension. figure 55 . 32- lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 12) dimensions shown in millimeters ordering guide model 2f 1 temperature range package description package option AD9106 bcpz ?40c to +85c 32 - l ead lfcsp _wq cp - 32 - 1 2 AD9106 bcpzrl7 ?40c to +85c 32-l ead lfcsp _wq cp-32-12 AD9106 - ebz evaluation board 1 z = rohs compliant part. ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11121 -0- 2/13(a) |
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